The present invention relates generally to a method of making staggered complementary heterostructure field effect transistors, and more particularly to a method to implement complementary circuits in group III/group V compound semiconductors.
During the last years, silicon CMOS circuits have become the leading technology in electronic systems. With significant advancement obtained in gallium arsenide (GaAs) and related compound materials, work on complementary circuits in these materials have become of interest and many companies and laboratories are advancing this technology. Best n-channel FETs have been demonstrated on InP substrates and it is desirable to develop complementary circuits in this technology.
CMOS technology, based on n- and p-channel Si FETs is well established. Complementary FET technology, based on GaAs material has been demonstrated in several laboratories, such as Honeywell SRC, IBM Research Center and AT&T Bell Labs. AT&T also demonstrated n- and p- channel devices in InGaAs channel structures on InP substrates. There exist several approaches for forming the transistors in the same layer structure. Honeywell pioneered the HIGFET approach where the same structure is used for both types of devices. Ion implantation is used to convert the basic structure into either an n- or p- channel device. In the selective regrowth approach one type of device is fabricated first. Then the area, allotted to the second type device is etched off and new material is selectively grown in this area. IBM is pursuing the stratified approach where material for both type devices is grown on top of each other. The top transistor is formed by implanting ohmic contact areas, forming ohmic contacts, and depositing the gates. The lower transistor is accessed by first etching off the material for the top transistor, then following the same procedure used for the top transistor. All complementary compound semiconductor ICs (Integrated Circuits) are currently in the research and development stage. The technology taught in this invention can be considered an extension of the HIGFET approach.
The following U.S. patents are of interest.
Sitch U.S. Patent No. 4,937,474 PA0 Xu et al U.S. Patent No. 4,899,201 PA0 Hsieh U.S. Patent No. 4,830,980 PA0 Abrokwah et al U.S. Patent No. 4,814,851 PA0 Abrokwah U.S. Patent No. 4,729,000
In particular, Abrokwah U.S. Patent No. 4,729,000 relates to a low power complementary (Al, Ga) As/GaAs heterostructure insulated gate field-effect transistor (HIGFET) wherein a pseudomorphic InGaAs semiconductor gate is used to reduce the HIGFET V.sub.t. This patent further discloses an embodiment wherein Si was used to create the n.sup.+ implanted regions and Mg or Be have each been used to form the p.sup.+ implanted regions. The HIGFET utilizes two epitaxial layers grown on a semi-insulating GaAs wafer. Similarly, see the Abrokwah et al U.S. Patent No. 4,814,851 and the Hsieh U.S. Patent No. 4,830,980. The Xu et al U.S. Patent No. 4,899,201 relates to improved p-channel FETs and discloses a heterostructure FET formed by a narrow band gap substrate such as GaAs, InGaAs, InP or GeSi and thin wide band gap layer of AlGaS, InAlAs or Si dependent upon the particular material used for the substrate. This patent further discloses a HIGFET which can be either a p-channel or an n-channel device depending on whether the source and drain are p.sup.+ or n.sup.+ conductivity. The Sitch U.S. Patent No. 4,937,474 contains a reference to substitution of Si or InP MESFETs, or JFETs, HEMTs, HIGFETs or SISFETs for GaAs MESFETs described in detail.